1. Technical Field
The present invention relates in general to a clock pulse generator and frequency multiplier and in particular to a delayed matching signal generator and frequency multiplier that is provided by using scaled delay networks for providing precisely delayed matching signals and multiplied frequency signals.
2. Description of the Related Art
It is well known and desirable at times to generate a higher frequency clock from a lower frequency clock. For example, such a higher frequency clock is required for synchronization between two chips that need to communicate with each other. Phase Locked Loop (PLL) based clock frequency multipliers are commonly used in microprocessors for generating the main processor clock from a lower frequency clock. It is generally known that a PLL takes the bus clock and multiplies it to a higher frequency. One problem is that the extreme performance requirements for these frequency multipliers generally warrant the use of complex PLLs since frequency synthesis PLLs (analog circuits) are typically difficult to design. A digital solution is generally desired since it is typically easier to design and migrates between technologies more easily. However, less critical timing applications, such as bus synchronization (communications between two chips), special clock recovery, and data re-timing systems, do not warrant such extreme performance requirements, and lower accuracy and reduced cost/design frequency multipliers may be able to be designed and used.
Delay Locked Loop (DLL) approaches are popular for some of these applications, but such techniques have drawbacks and limitations, such as having to maintain a relatively short delay due to possible increases in power supply sensitivity, requirements of special initialization protocol, longer acquisition time, and inability to provide frequency multiplication.
There exist dynamic circuits or devices which require the generation of a reset signal. For example, the reset signal is able to be used for resetting a signal capture and latch process or other such processes. Conventional and prior art approaches involve delay techniques which produce reset pulse widths that are independent of clock frequency but which are also highly dependent on process, temperature, and supply voltage. The operating frequency of these circuits or devices using conventional reset generation is limited since the reset portion of the period may become too large compared to the evaluation portion as the period time is reduced. In examining a cycle of a clock period, the evaluation period and the reset period must be compared. The reset must be set for a minimal period of time, such as a set percentage (i.e. 10%) of the cycle. If the frequency is increased, the reset portion of the clock cycle may become a larger percentage of the cycle.
Also, it is well known in the art to generate a reset signal for a clock signal by simply using and delaying the clock signal by a delay value. However, if the frequency of the clock signal increases (i.e. period decreases) and the delay of the clock signal for generating the reset signal is not adjusted in any way, then the reset signal portion of the period may become too large compared to the evaluation period. Conversely, if the frequency of the clock signal decreases (i.e. period increases) and the delay of the clock signal for generating the reset signal is not adjusted in any way, then the reset signal portion of the clock period may become too small, and the reset signal may extend over into the next period or cycle of the clock signal. Thus, matching the delay of the clock signal for generating the reset signal in proportion to the period or frequency of the clock signal is highly advantageous and desirable.
It is therefore advantageous and desirable to provide a delayed matching signal generator for generating a delayed matching signal from an input signal wherein the delayed matching signal generator uses, matches, and more precisely controls a delay of the input signal in proportion to the period or frequency of the input signal in generating the delayed matched signal. It is also advantageous and desirable to provide a reset signal generator for generating a reset signal from a clock input signal wherein the reset signal generator uses, matches, and more precisely controls a delay of the clock input signal in proportion to the period or frequency of the input signal in generating the reset signal. It would be further advantageous and desirable to use the delayed matching signal generator for using, matching, and more precisely controlling a delay of a signal for generating more precisely delayed matched signal(s) wherein the signal and the delayed matched signal(s) may be used to generate a multiplied frequency signal. It is also advantageous and desirable to provide improved and better systems and methods of generating a higher frequency clock from a lower frequency clock. It is still also advantageous and desirable to provide relatively simple and inexpensive systems and methods for generating such higher frequency clock from a lower frequency clock.